1. Field of the Invention
The invention pertains generally to a method for fabricating devices in III-V semiconductor substrates, as well as the resulting devices.
2. Art Background
A wide variety of devices, including discrete electronic devices, discrete opto-electronic devices (devices which produce an optical output in response to an electrical input, or vice versa), as well as integrated circuit and integrated optical devices, are now being fabricated, or have been proposed for fabrication, in substrates which include III-V semiconductor materials, because these materials exhibit a number of significant advantages. (A III-V semiconductor material, for purposes of this disclosure, is a semiconductor which includes Group III and Group V elements.) Included among these advantages is the fact that the mobility of electrons in the III-V semiconductor materials is much higher than in other semiconductor materials, such as silicon. As a consequence, electronic and opto-electronic devices, e.g., discrete transistors, lasers and integrated circuit devices, fabricated in the III-V semiconductor materials are capable of achieving much higher operating speeds than are the corresponding devices fabricated in, for example, silicon. In addition, the III-V semiconductor materials are direct bandgap materials, rather than indirect bandgap materials, as is the case with silicon. As is known, stimulate emission of light is only achievable in the former type of materials. Consequently, opto-electronic devices which depend, for their operation, on stimulated light emission, e.g., lasers, must be fabricated in direct bandgap materials. Moreover, direct bandgap materials exhibit much higher quantum efficiencies than indirect bandgap materials, and therefore the former materials are preferred for the fabrication of optical detector, optoelectronic devices, such as avalanche photodiode (APD) detectors.
The various types of devices fabricated in III-V semiconductor substrates include a variety of device components, such as active regions (a region of semiconductor material in a light-emitting opto-electronic device from which most of the light is emitted), sources, drains, p-n junctions and heterojunctions. (The term heterojunction, as used in this disclosure, denotes the interface between two semiconductor materials having different compositions or different doping levels.) Each such device also includes one or more metallic wires or metallic runners, generally fabricated from gold (Au), terminating in one or more non-rectifying, low specific contact resistance (LSCR) electrical contacts to the substrate, through which electrical signals are communicated to the device. (As used herein, the term non-rectifying, LSCR electrical contact denotes an electrical contact which permits electrical current flow in two opposed directions across the contact, and exhibits a specific contact resistance less than or equal to about 10.sup.-4 ohm-cm.sup.2 in both directions. Significantly, such contacts to III-V semiconductor substrates are essential because the gold (per se) in the gold wires and gold runners yields a rectifying, rather than non-rectifying, electrical contact to III-V semiconductor materials.)
A non-rectifying, LSCR electrical contact to a III-V semiconductor substrate is conventionally formed by depositing, e.g., e-beam evaporating, a region of material which includes gold and a p-type (e.g., zinc or beryllium) or n-type (e.g., tin or germanium) dopant (depending upon whether the underlying semiconductor material is of p-type or n-type conductivity) onto the substrate. Because ultra-high-vacuum conditions are typically not employed, a native oxide (or oxides) of the semiconductor material tends to form on the surface of the substrate during the deposition procedure. Such native oxides are generally undesirable because their presence serves to increase specific contact resistance. Although the surface of the substrate is typically cleaned to remove these oxides, it is generally acknowledged that complete removal of the oxides is impossible. However, the presence of these oxides does not, in this instance, preclude the formation of a LSCR electrical contact. That is, after deposition, the gold-and-dopant-containing region is alloyed at temperatures as high as about 450 degrees Centigrade (C) for periods of time equal to about 7 minutes. Significantly, it is believed that this alloying procedure serves to drive the dopant through the native oxide (or oxides) and into the substrate, and electrically activate the dopant, to produce an electrical contact having a low specific contact resistance.
While the above alloying procedure does produce useful, non-rectifying, LSCR electrical contacts, this procedure does have a number of disadvantages, including undesirable interactions between the gold and the semiconductor substrate. For example, the relatively high temperatures involved in the alloying process result in the gold diffusing into the substrate, causing decomposition of the substrate material. As a consequence, and if, for example, the substrate material includes indium phosphide (InP), then the resulting free In and P (freed by the decomposition of the InP) tend to diffuse to the surface of the electrical contact, where they may undergo oxidation to form electrically insulating layers. In addition, the relatively high alloying temperatures also result in upward diffusion of the p- or n-type dopant to the surface of the electrical contact, where the dopant also tends to become oxidized to form an electrically insulating layer. Unless great care is taken to remove these insulating layers, the electrical contact will exhibit undesirably high series resistance.
The downward diffusion of gold into the substrate is also undesirable because the presence of gold in, for example, an active region constitutes a non-radiative recombination center, which serves to reduce the useful lifetime of light-emitting opto-electronic devices, such as lasers. In addition, the downward diffusion of gold into a substrate containing a relatively shallow p-n junction (a p-n junction having a depth equal to or less than about one-half micrometer) is undesirable because the gold penetrates through, and thus short circuits, these relatively shallow p-n junctions.
The relatively high alloying temperatures employed in forming the gold electrical contacts are further disadvantageous because they sometimes lead to significant, differential thermal expansions of the materials covering the substrate, which in turn leads to high stress in the substrate. Such high stress is undesirable because it leads to bending of the substrate, which makes conventional lithographic processing very difficult, if not impossible. This high stress often also leads to cracking and/or peeling of material layers overlying the substrate.
The above contact-fabrication procedure is further disadvantageous because it requires that the relative amounts of gold and dopant be precisely controlled to achieve the eutectic composition. Otherwise, the gold may not melt during the alloying process and/or the alloying process may not produce a sufficient or desired interaction between the dopant and the substrate, leading to an undesirably high specific contact resistance.
The above-described problems, resulting from the undesirable interactions between gold and III-V semiconductors, as well as scientific curiosity, have led to investigations of the interactions between various metals, including nickel, and III-V semiconductor substrates, such as InP. (Regarding these investigations see E. Hokelek et al., "A Study of Schottky Contacts on Indium Phosphide", Journal of Applied Physics, Vol. 54, No. 9, September 1983, pp. 5199-5205 and G. J. Hughes et al., "Nickel and Copper on Cleaved Indium Phosphide: Structure, Metallurgy and Electronic Properties, " Journal of Physics C: Solid State Physics, Vol. Properties", Journal of Physics C: Solid State Physics, Vol. 16 (1983), pp. 2391-2405.) In these investigations, the various metals were deposited onto indium phosphide substrates cleaved under ultra-high-vacuum conditions to avoid adsorption of contaminants, such as carbon and oxygen (which might increase specific contact resistance, or preclude the formation of non-rectifying contacts). As a result of these investigations, it was concluded, among other things, that nickel produces a Schottky barrier contact (a rectifying, metal-semiconductor contact) to InP and, moreover, that a relatively thin nickel phosphide layer is formed at the interface between the nickel and the InP. While no connection was made (in these investigations) between the existence of the nickel phosphide layer and the existence of the Schottky barrier contact, it has long been believed that a non-rectifying, LSCR contact between a metal, such as nickel, and a substrate of InP can only be achieved if the metal InP interface is rich in indium. But the interfacial nickel phosphide layer found in the investigations was, presumably, the result of nickel reacting, i.e. combining, with the phosphorus in the InP substrate. Such a reaction would necessarily produce free indium (In), which (under the resulting In concentration gradient) would diffuse to the surface of the nickel, resulting in a nickel-InP interface which is depleted of In. Significantly, a substantial amount of In was found (presumably the result of upward diffusion) on the surface of the nickel, in these investigations. Consequently, and on the basis of current beliefs, an In-depleted interface, produced by the formation of an interfacial, nickel phosphide layer, would preclude the formation of a non-rectifying, LSCR contact, and would be consistent with the Schottky barrier contacts found in the investigations.
Thus, those engaged in the development of III-V semiconductor devices have sought, and continue to seek, new materials and new methods for forming non-rectifying, LSCR electrical contacts to III-V semiconductor substrates.